PIC16F74T-I/ML【PDF 77/104 页】IC MCU FLASH 4KX14 A/D 44QFN

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Sheet目录3882

73页 74页 75页 76页 [77页]78页 79页 80页 81页

Micrel, Inc.

KSZ8851-16MLLJ

March 2010

M9999-030210-1.0

MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0

The 64-bit MAC address table is used for group address filtering and it is enabled by selecting item 5 “Hash perfect” mode

in Table 3 (Address Filtering Scheme). This value is defined as the six most significant bits from CRC circuit calculation

result that is based on 48-bit of DA input. The two most significant bits select one of the four registers to be used, while

the others determine which bit within the register.

Multicast table register 0.

Bit

Default Value

R/W

Description

15-0

0x0

HT0 Hash Table 0

When the appropriate bit is set, if the packet received with DA matches the CRC, the

hashing function is received without being filtered.

When the appropriate bit is cleared, the packet will drop.

MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1

Multicast table register 1.

Bit

Default Value

R/W

Description

15-0

0x0

HT1 Hash Table 1

When the appropriate bit is set, if the packet received with DA matches the CRC, the

hashing function is received without being filtered.

When the appropriate bit is cleared, the packet will drop.

Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1, all

multicast addresses are received regardless of the multicast table value.

MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2

Multicast table register 2.

Bit

Default Value

R/W

Description

15-0

0x0

HT2 Hash Table 2

When the appropriate bit is set, if the packet received with DA matches the CRC, the

hashing function is received without being filtered.

When the appropriate bit is cleared, the packet will drop.

Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1, all

multicast addresses are received regardless of the multicast table value.

MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3

Multicast table register 3.

Bit

Default Value

R/W

Description

15-0

0x0

HT3 Hash Table 3

When the appropriate bit is set, if the packet received with DA matches the CRC, the

hashing function is received without being filtered.

When the appropriate bit is cleared, the packet will drop.

Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1, all

multicast addresses are received regardless of the multicast table value.

0xA8 – 0xAF: Reserved

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